Efforts in the design of integrated circuits for radio frequency (RF) communication systems generally focus on improving performance, reducing cost or a combination thereof. One area of particular interest relates to frequency synthesis. Presently there are two main approaches to frequency synthesis, one being analog, the other being primarily digital.
The analog approach generally employs a phase-locked loop (PLL) that provides a desired frequency signal based on a comparison of the output of a voltage-controlled oscillator (VCO) with a defined phase of a reference signal. Error correction is implemented in response to errors associated with the output of the PLL. A phase frequency detector can detect errors and adjust the output to a desired carrier frequency. This approach further employs a loop containing a PLL and a programmable divide-by-N upconverter that multiplies the stable frequency. A loop filter is typically utilized to help suppress spurious signals so as to mitigate undesired frequency modulation in the VCO. PLL-based frequency synthesizers generally have a noise level inversely proportional to the interval required to slew and settle to a new (tuned) frequency. As a result, use of PLL-based synthesizers in fast-hopping systems requires compromises.
The other main type of frequency synthesizer is a direct digital synthesizer (DDS). The DDS approach generally employs logic and memory components to digitally construct a desired output signal. A digital-to-analog converter (DAC) converts a corresponding digital output signal to the analog domain. Consequently, the DDS generally is restricted to operate within frequencies supported by the DAC. Additionally, this type of synthesizer tends to be limited in spur size, as the linearity of multi-bit DACs is limited and degrades as the operating speed increases